Building Post-layout Performance Model of Analog/RF Circuits by Fine-tuning Technique

Zhikai Wang1, Wenfei Hu1, Jingbo Zhou2, Wenyuan Zhang3, Ruitao Wang4, Jian ZHang5, Dejing Dou6, Zuochang Ye5, Yan Wang7
1School of Integrated Circuits´╝îTsinghua University, 2Baidu Research, Business Intelligence Lab, 3Beijing Institute of Technology, 4Shool of Integrated Circuits, Tsinghua University, 5School of Integrated Circuits, Tsinghua university, 6Big Data Lab, Baidu Research, 7School of Integrated Circuits, Tsinghua University


Abstract

Although schematic-level optimization methods have been well studied in the literature, limited to layout generation and parasitic extraction, few tools can provide reliable post-layout level optimization of analog/RF post-layout. In fact, in order to quickly identify feasible regions and avoid unnecessary simulations during sizing optimization process, the surrogate model which can predict post-layout simulation performance metrics must be built. However, building a accurate model is yet a challenging task because of the conflict between sufficient samples and expensive simulation costs. Fortunately, schematic simulation costs are more cheaper than post-layout simulation costs, and certain similarities of circuit behaviors exist in between the schematic and post-layout simulation stage. Motivated by these observations, we propose a Fine-tuning based Model Fusion (FMF) technique to reuse some knowledge from early data. We first copy a pre-trained Artificial Neural Networks (ANN) model parameters which is carefully trained by abundant schematic-level samples, and fine-tune this model by few post-layout samples. Then, the number of post-layout samples required for training can be greatly reduced. Finally, we conduct experiments on three different analog/RF circuits and verify the efficiency of FMF. FMF can achieve a more than 9x sample reduction and highest modeling accuracy over traditional modeling techniques.