FastMem: A Fast Architecture-aware Memory Layout Design

Alok Parmar1, Kailash Prasad2, Nanditha Rao1, Joycee Mekie2
1International Institute of Information Technology, Bangalore, 2Indian Institute of Technology, Gandhinagar


Memory design can be an extremely challenging and time-consuming task, which includes several exploratory studies to find the most optimal size of the array. Thus, to speed up the memory design, it is imperative that low-level circuit details should be masked when doing architectural analysis. In this paper, we propose FastMem - an approach that allows designers to obtain memories with the highest area-efficiency (AE) and least energy-delay product (EDP) using an architectural tool (CACTI), which can then be fed to a memory compiler to obtain the final layout. We use FastMem to obtain optimal memory configurations for 65nm, 32nm, and 7nm technology nodes. As part of the experiments, we observe that, as technology scales from 65nm to 32nm to 7nm, the contribution of peripherals and interconnects to the access time increases from 32% to 70%. Thus, at lower technology nodes, we need to optimize the peripherals and interconnects rather than the actual SRAM cells. FastMem allows us to study the near-threshold operation and 8T SRAM configuration as well. We introduce a metric called the Figure of Metric (FOM= AE/EDP) and show that increasing the number of banks for large-sized memory arrays improves the FOM by nearly 33%. Lastly, FastMem shows that a square (or near-square) sub-array results in 75% higher FOM as against skewed sub-arrays for bulk CMOS technology, whereas a skewed sub-array result in optimum performance for the FinFET technology node.