Monolithic 3D (M3D) integrated circuits (ICs) provide ultra-high device density compared to through-silicon via (TSV) based 3D integration owing to the sequential fabrication process. Thus, M3D can effectively sustain Moore’s law without relying on costly technology shrinking. Nevertheless, the heat dissipation problem in M3D ICs raises a great challenge and is different from TSV-based counterparts due to strong thermal coupling between neighboring tiers. We firstly design the transistor-level partitioned circuits enabled by M3D integration in the 45 nm technology node. Then, we perform the thermal evaluations for M3D circuits with a thermal model based on the finite element method. Experimental results show that the peak and average temperatures of M3D ICs are respectively 1.0-3.7X and 1.0-5.4X higher than those of the 2D counterparts. Their peak temperatures can be reduced by 7K when considering the thermal conductivities of monolithic inter-tier vias (MIVs). Finally, we evaluate the impact of the MIV distribution topology as well as the thickness of the inter layer dielectric (ILD) on thermal dissipations of M3D ICs.