The growing popularity of embedded systems in wide range of applications demands ever greater number of features integrated onto a single SoC to reduce the overall system cost. This high level of integration leads to higher power dissipation, increased thermal system cost, degraded performance and reduced battery life. To tackle these challenges, SoC should be architected and designed with a holistic view in context of its usage in the embedded systems. Picking the right knee point of performance and power curve and simplifying operating conditions is key. This paper presents some novel approaches and techniques developed on a next generation high performance multi-core Sitara MPU device from Texas Instruments.