EFCSA: An Efficient Carry Speculative Approximate Adder with Rectification

Saurabh Singh1, Vishesh Mishra1, Sagar Satapathy2, Divy Pandey1, Kaustav Goswami3, Dip Sankar Banerjee2, Babita Jajodia1
1Indian Institute of Information Technology Guwahati, 2Indian Institute of Technology Jodhpur, 3University of California Davis


Approximate computing offers the flexibility to trade-off accuracy for computational speed, reduced power consumption, and lesser on-chip area. Such techniques have accumulated extensive attention in recent times as these can be used in most error-resilient applications. Although several approximate adder designs have been proposed in the past, there still exists scope for further improvement. Existing state-of-the-art designs often involve a trade-off between the margin of acceptable error and its Quality of Results (QoR). This paper proposes an approximate adder with higher accuracy and better QoR for error-resilient applications called an efficient reconfigurable carry speculative approximate adder with rectification, or simply EFCSA adder. Its reconfigurable sister version, called REFCSA adder, is inherently reconfigurable, allowing accurate configuration during runtime. The proposed design aims to limit the carry chain's length in the conventional ripple carry adder (RCA) using a block-based mechanism. EFCSA showcases results that are 12.3x faster than the conventional RCA. On average, the adder is 45.1% more accurate and has 31.97% better power-delay-product (PDP) than several existing state-of-the-art approximate designs.