Functional Level Abstraction and Simulation of Verilog-AMS Piecewise Linear Models

SADIA AZAM1, Nicola Dall'Ora2, Enrico Fraccaroli3, Franco Fummi4
1University of Verona ,italy, 2University of Verona, 3Università degli Studi di Verona, 4Universita' di Verona


In electronic design and testing, the simulation speed of analog components is crucial. Moreover, the simulation of heterogeneous components embedded in a Virtual Platforms (VP) needs to be fast and accurate. Often, the analog components are non-linear, and simulating them is not easy to ensure the model’s convergence. In this context, techniques for simulating linear circuits are stable and efficient, but there are still many research gaps for non-linear circuits. There are no systematic methods available to solve non-linear equations efficiently. One standard method is to solve these non-linear equations by describing them as a piecewise linear (PWL) models. PWL techniques approximate non-linear functions with a set of linear functions. This is common to most solver methods: they linearize to compute an inverse matrix, finding which direction to move to satisfy the equations.

In this article, an abstraction methodology for PWL models is proposed. By using this methodology, it is possible to abstract a piecewise model described with the Verilog-AMS language to the C++ language. These C++ models can be integrated into VPs. A half wave rectifier and memristor models are selected to explain and validate the methodology. Furthermore, to show the effectiveness of the proposed technique, the abstracted model of the half wave rectifier is integrated into a MEMS accelerometer. Moreover, the accelerometer is integrated into a VP to show the effectiveness of the functional simulation.