Examining Vulnerability of HLS-designed Chaskey-12 Circuits to Power Side-Channel Attacks

Saya Inagaki1, Mingyu Yang1, Yang Li2, Kazuo Sakiyama2, Yuko Hara-Azumi1
1Tokyo Institute of Technology, 2The University of Electro-Communications


In this paper, a dedicated circuit of Chaskey-12, a lightweight message authentication code algorithm suitable for resource-constrained devices, was implemented on FPGAs. Four different versions of the Chaskey-12 circuit were generated using high-level synthesis (HLS) with different optimizations for memory and operation parallelization to examine the effects not only on the circuit area and execution time but also on vulnerability to power side-channel attacks. We evaluated power traces of the four versions with Welch's t-test to disclose that their power consumption depends on the processed data (i.e., plaintext and key), implying that they are all vulnerable to power analysis attacks when no countermeasure is employed. Besides, we clarified two useful findings of HLS optimizations; (1) even for cryptographic algorithms with low memory usage like Chaskey-12, memory optimization can have impacts enough to leak information, and (2) logic optimization to extract operation parallelism has a further greater impact on leakage.