Design methodology for scalable 2.5D/3D heterogenous tiled chiplet systems

srivatsa rangachar srinivasa1, Jainaveen Sundaram Priya2, Dileep Kurian3, Erika Ramirez Lozano1, Satish Yada1, Saransh Chhabra1, Kamakhya Prasad Sahu4, Paolo Aseron1, Ronald Kalim1, Tanay Karnik4, Anuradha Srinivasan4
1Intel Labs, 2Intel Corporation, 3Intel technologies, 4Intel


The incentives for chiplet based systems have been multifold especially with ever growing workload requirements, heterogeneous integration, and rising cost of technology downscaling. This process is commonly known as die disaggregation where multiple functional chiplets are integrated on an interposer to form a bigger complex system. Current approaches are agnostic of the attachment technologies and still use monolithic design methodology for independent chiplet design and integration. Individual chiplets are mostly optimized for a specific product and designed with no intent of reusability. Today`s application trends demand these tiled systems to support co-existing chiplets with different technology nodes and different inter-die-interconnect requirements. In this paper, we describe the methodology aspects of co-designing functional chiplets, interposer and package level interconnects. We describe the advantages of chiplet reusability and establishing high throughput inter die connectivity.