The migration of critical workloads into the cloud and the introduction of new services processing large amounts of data is motivating a need for purpose-built (AI/ML) fabrics that will require new scale-up and scale-out compute and networking architectures. Furthermore, as the ratio of AI workloads to standard workloads increases, memory utilization is emerging as a key factor in infrastructure total cost of ownership (TCO). Silicon Photonics Chiplets in Package (SCIP) interconnect technology platforms promise to remove both copper reach limitations and the optical I/O bandwidth density bottlenecks thereby enabling memory disaggregation, memory pooling and composable architectures to improve memory utilization efficiency and optimize TCO. In this paper, we present the performance of the SCIP I/O and provide vectors of scaling to meet the next generation compute needs.