High-performance heterogeneous computing systems are suitable for big-data applications. However, the use of off-chip interconnects (e.g., PCIe in discrete CPU and GPU based systems) lead to relatively poor performance. Heterogeneous architectures where the different cores are connected via Network-on-Chip (NoC) can solve this problem. The use of Three-dimensional (3D) integration can further reduce this communication problem. 3D integration has frequently been described as a means to overcome scaling bottlenecks, and advance both “More Moore” and “More Than Moore” through the use of vertical interconnects and die/wafer stacking. In this paper, we present both the advantages and the various design challenges in 3D-enabled heterogeneous manycore systems