Abstract—High data rate detectors play an integral part in scientific research and their development is actively pursued at High Energy Physics (HEP) facilities around the world. Edge Machine Learning (ML) offers the ability to reduce data rates by integrating ML algorithms into Application Specific Integrated Circuits (ASICs) on the front end electronics. In this work, we explore a set of neural network architectures for predicting the peak amplitudes in the detector’s sensor response.We have designed and synthesized several MLP based neural networks comparing their inference accuracy, power consumption,and area targeting for minimal latency. The neural networks are synthesized in a commercial 65nm process. The effect of quantizing the network’s weights and biases on hardware performance and area is reported. We also conduct design space exploration to compare between design alternatives in terms of accuracy, power,performance, and area