High-level synthesis (HLS) has significantly reduced time and complexity of the hardware design by raising the abstraction to high-level languages (HLL) like C/C++. HLS has not only allowed non-hardware engineers to quickly prototype and test their algorithmic flow but has also enabled hardware developers to build hardware quicker for emerging algorithmic designs such as machine learning (ML) and artificial intelligence (AI) networks. However, current HLS tools were not designed with security in mind as they only optimize the design for area, power, time, and throughput. As a result, security vulnerabilities may be introduced in the HLS-generated RTLs unintentionally. In this paper, we discuss some of the optimizations performed by HLS and present bad design coding practices in HLL that could lead to security vulnerabilities in the RTL. We also explore potential solutions, their limitations, and challenges moving forward to bring attention towards development of automated verification tools and guidelines to ensure secure HLS translation