Infineon Platform for SoC IO Ring and Package Design

Sathvik Tarikere Sathyanarayana1, Anna-Antonia Berger2, Mahesh Simpy Kumar3, Akbay Erkan2, Ramkrishna Paira3
1Infineon Technologies Pvt Ltd, 2Infineon Technologies AG Neubiberg, Germany, 3Infineon Technologies India Pvt. Ltd, Bangalore, India


The Goal of the methodology is for defining pad/port connectivity, the I/O ring and ball-outs (bumps). Along with the support for wire bond packaging technology, the platform also supports flip chip packaging features such as hard macros/3rd party IPs and n-to-m relationships between pads and bumps. The methodology provides complete automation for I/O fabric and netlist generation in the chip design cycle. This methodology by automatically generating and validating the I/O fabric from single source specification can ease SoC I/O integration significantly, drastically reducing time to market time with an added advantage of eliminating design bugs.