Physical Unclonable Functions (PUFs) are lightweight security primitives that exploit complex manufacturing variations in integrated circuits to extract secret keys. It is well-established that the unique keys generated by the mux-based arbiter PUF can be predicted accurately using logistic regression (LR), provided a set of challenge-response pairs (CRPs) are known. The integration of 28nm HKMG FeFET with CMOS technology has been shown to neither alter the switching behavior of the FeFET, nor affect the baseline CMOS. In this work, we present simulation results that discuss the possibility of using the FeFET to design “stronger” arbiter PUFs that can be reconfigured at least 6n times, where n represents the number of stages. Results from LR based attacks suggest that the training dataset may need to be updated after every reconfiguration cycle, preventing the adversary from collecting enough training data for each configuration within a reasonable amount of time for a security breach.