On the Correlation Between Resource Minimization and Interconnect-related Complexities in High-Level Synthesis

Shantanu Dutt1, Xiuyan Zhang1, Ouwen Shi2
1University of Illinois at Chicago, 2Cadence Design Systems


As the technology node advances to sub-10nm, two interconnect-centric metrics of a circuit, the interconnect complexity (wirelength/WL) and congestion, become more and more important across all design stages alongside conventional resource or function-unit (FU)-centric metrics like timing, leakage power and area of a VLSI design. High-level synthesis (HLS), as one of the earliest design stages, rarely monitors the two interconnect-metrics, which makes their recovery at later stages very hard, resulting in a sub-optimized or even unrouteable design. HLS algorithms and tools typically perform FU-centric minimization via operation scheduling, module selection and binding. As a consequence, it overlooks interconnect complexity and congestion. In this paper, we explore the correlation between the FU- centric optimization and the corresponding interconnect and congestion metrics. This provides an overview of how conforming HLS optimization impacts interconnect and congestion metrics.