Flash ADC Utilizing Offset Voltage Variation With Order Statistics Based Comparator Selection

Takehiro Kitamura, Mahfuzul Islam, Takashi Hisakado, Osami Wada
Kyoto University


High-speed flash ADCs are required for wireless communication systems. However, the trade-off between area, power and linearity suffers severely by offset voltage variation in sub-micron process. In this paper, we propose a flash ADC architecture that utilizes the offset voltage variation to
reduce area and power consumption by eliminating reference generation. The proposed architecture utilizes offset voltages as references by selecting the appropriate comparators after an on-chip calibration. The on-chip calibration is performed based on order statistics that allows to evaluate offset voltages in the time-domain. We verify our proposed architecture by HSPICE simulation based on a commercial 65~nm process. Our proposed architecture realizes a 5-bit ADC with power consumption of less than 1~mW at 2~GS/s of operation excluding the encoder.