State retention storage is indispensable in power gated circuit since the circuit state should be saved somewhere before sleeping so that the circuit can continue the execution from the saved state when waking up. Thus, it is essential to allocate the always-on retention storage minimally to reduce the leakage power. Recently, it is demonstrated that a substantial saving on total retention storage can be achieved simply by allowing some flip-flops to retain 2 or 3 bits if needed, as opposed to strictly allocating every flip-flop to retain exactly 1 bit. In this work, we propose an optimal solution to the problem of allocating state retention storage, constraining the size of every flip-flop’s retention storage never to exceed k bits where k is 2 or 3. Specifically, we transform the allocation problems constraining the wakeup latency constraint k to 2 and 3 clock cycles into unate covering problems and solve them optimally with three objective options: minimizing total bits of retention storage, directly minimizing total leakage power consumed by retention storage, and minimizing total implementation area of retention storage. Through experiments with benchmark circuits, it is shown that our optimal algorithm is able to further reduce the total bits of retention storage up to 3.42%, the leakage power on retention storage up to 9.91%, and the retention storage area up to 4.46% while k is set to 3 over that produced by the conventional best-known allocation heuristic.