On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays

Hsin-Tsung Lee1, Chia-Chun Lin1, Yung-Chih Chen2, Chun-Yao Wang3
1National Tsing Hua University, 2Yuan Ze University, 3Dept. CS, National Tsing Hua University


Memristors are considered as promising candidates for Computation-In-Memory due to their non-volatile storage and computing capabilities. In recent years, a growing number of general-purpose computing platforms based on different design styles at the memristor crossbar arrays have been proposed. In this paper, we present a comprehensive synthesis approach for performing arbitrary Boolean logic operations in area-constrained crossbar arrays. The approach exploits multicycle logic operations to deal with the delay and area constraints. The experimental results on ISCAS'85 benchmarks show that our approach can effectively reduce the overhead of one-row readout constraint, which needs many cycles to move data. Our approach is also capable of performing operations parallel in both row and column directions. The experimental results at larger EPFL benchmarks show that our approach is robust and scalable.