ChaoLock: Yet Another SAT-hard Logic Locking using Chaos Computing

Hadi Mardani Kamali1, Kimia Zamiri Azar1, Houman Homayoun2, Avesta Sasan1
1George Mason University, 2University of California Davis


In this paper, we explore the possibility of exploiting chaos computing as a new means of logic locking. We introduce the concept of chaotic logic locking, called ChaoLock, in which, by leveraging asymmetric inputs in digital chaotic Boolean gates, we define the concept of programmability (key-configurability) to the sets of underlying initial conditions and system parameters. These initial conditions and system parameters determine the operation (functionality) of each digital chaotic Boolean gate. Also, by proposing dummy inputs in chaotic Boolean gates, we show that during reverse-engineering, the dummy inputs conceal the main functionality of the chaotic Boolean gates, which make the reverse-engineering almost impossible. By performing a security analysis of ChaoLock, we show that with no restriction on conventional CMOS-based ASIC implementation and with no test/debug compromising, none of the state-of-the-art attacks on logic locking, including the SAT attack, could reformulate chaotic Boolean gates while dummy inputs are involved and their parameters are locked. Our analysis shows that even a low proportion of chaotic Boolean gates mixed with CMOS digital gates can guarantee resiliency against the state-of-the-art attacks on logic locking at low overhead.