A Wafer-scale Manufacturing Pathway for Fine-grained Vertical 3D-IC Technology

Sachin Bhat, Sounak (Shaun) Ghosh, Sourabh Kulkarni, Mingyu Li, Csaba Andras Moritz
UMass Amherst


Three-dimensional integrated circuits (3D-ICs) provide a feasible pathway for scaling CMOS technology in the foreseeable future. IMEC and IRDS roadmaps project that 3D integration is a key avenue for the IC industry beyond 2024. They project that some form of 3D-IC technology based on nanosheets/nanowires is likely to become mainstream soon. SkyBridge-3D-CMOS (S3DC) is one among the first vertical nanowire-based fine-grained 3D-IC directions which offers paradigm shift in technology as well as design. Rather than die-die and layer-layer stacking, S3DC’s core aspects, from device to circuit style to interconnect, are co-architected in a 3D fabric-centered manner building on a uniform 3D nanowire template. Nanowire-based 3D-IC technologies such as S3DC solve most of the traditional scaling issues of 2D-CMOS but present new manufacturing challenges because of their complex 3D geometry. Therefore, for these directions to become mainstream, a robust wafer-scale manufacturing pathway that addresses these challenges is vital. In this paper, we propose a wafer-scale manufacturing pathway aimed at developing and optimizing the manufacturing process flows of S3DC. Using physics-driven virtual process integration functionalized with design and process parameters, we obtained realistic 3D structures for all the underlying IC elements and finally combined them to build 3D standard cells in S3DC. Electrical characterization of resultant structures using process and device simulations were performed while considering the material properties and nanoscale physics effects. Circuit-level simulations accounting for device behavior using SPICE-compatible compact model and circuit interconnect parasitics were carried out to study the impact of variations in process steps such as patterning, lithography, etch, deposition on device and interconnect performance. Our bottom-up simulation results indicate that the proposed pathway is robust enough to be adopted for large-scale production thus paving the way for wide-spread adoption of vertical fine-grained 3D-IC technologies.