Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis

Aneesh Balakrishnan1, Dan Alexandrescu1, Maksim Jenihhin2, Thomas Lange1, Maximilien Glorieux1
1IROC Technologies, 2Tallinn University of Technology


As the circuit implementation predominantly focuses on the higher density and performance with the technology scaling, more adverse types of faults and effects have been investigated by the system designers. Naive and compatible testing approaches are required to apprehend the emerging technological issues, and that will ensure high reliability and quality to the systems' functional behaviors. The unidentified permanent faults, in particular stuck-at faults, have very adverse impacts on the functional quality of circuits under stressful workloads. This paper focuses on the single stuck-at faults simulation and proposing an Artificial-Intelligence (AI) based algorithm for the prediction of Functional Failure Rate (FFR) of each net (netlist wire) for a given set of input patterns. The statistical prediction also provides an improved way of estimating the Functional Fault Coverage (FFC) and the effectiveness of the input test vector. The introduced algorithm is an accelerated methodology which will significantly reduce the time complexity by 60%, while compared to the traditional exhaustive fault-injection approaches. The case study has been conducted with the gate-level circuit of the 10-Gigabit Ethernet MAC.