Achieving Zero ADC Production Test Time with Self-calibration and BIST

Maher Sarraj, Haydar Bilhan, Wahed Mohammed
Texas Instruments, Inc.


There is a widespread trend to reduce and even eliminate analog IP production test time specially ADCs because of the need to add special components on the ATE tester board and the tester time cost. We developed a 12 bit 4 MSPS SAR ADC in 16 nm TSMC FinFET process with on-chip self-calibration to trim the mismatches of the capacitor arrays (Both single ended and differential) to better than 12 bit resolution. In addition, the ADC IP will include an internal precision reference system which also self-calibrate and generates the needed voltage level for the calibration steps. This eliminates the need for any off-chip references and reduces the complexity of the tester board significantly. Once the ADC is calibrated, internal built in self tests (BIST) are executed to verify basic ADC functionalities. As a result, the ADC will not require any production test time and will therefore reduce SOC cost. The ADC measures 750 nm x 600 nm, achieves 72 dB SNR and consumes 5 mW.