PVT and Aging Degradation Invariant Automated Optimization Approach for CMOS Low-Power High-Performance VLSI Circuits

Hema Sai Kalluru1, Prasenjit Saha2, Andleeb Zahra2, Zia Abbas3
1IIIT Hyderabad, 2International Institute of Information Technology Hyderabad, 3International Institute of Information Technology (IIIT), Hyderabad


In this paper, we aim at optimizing the leakage power and propagation delays using optimization algorithms like Glowworm Swarm Optimization and Neighbourhood Cultivation Genetic Algorithm, subjected to variations in Process, Voltage, Temperature and Aging degradation (PVTA) targeting low power or high performance applications. For high performance applications, we synthesize transistor sizes, at which the critical path delay in worst case PVT conditions with 3 years of NBTI aging degradation is optimized below the critical path delay (of initial sizing) at nominal conditions keeping power budget in bound. On the other hand, for low power applications, we obtain transistor sizing where leakage is reduced by more than 50%, keeping a bound on critical path delay. We have also proposed a step by step optimization method for optimizing complex cells. All the pre and post stress simulations are performed using HSPICE for 22nm Metal Gate High-K dielectric model parameters. The temperature range and the supply voltage ranges are -55 °C to 125 °C and 0.72V to 0.88V respectively. The process parameters are considered at ±3σ variation. The ingenuous working of the circuits for the obtained sizing is ensured by Monte Carlo analysis evaluating over entire range of process variations and operating conditions for the intended life time.