Fast Thermal Goodness Evaluation of a 3D-IC Floorplan

Satya K. Vendra and Malgorzata Chrzanowska-Jeske
Portland State University


High and uneven 3D chip temperatures can be reduced when appropriate thermal-aware design is incorporated in early floorplanning stage. We developed a fast approach to enable fast thermal goodness evaluation of 3D floorplans. The proposed algorithm uses a power-based measure calculated using the impact of the heat from adjacent intra and inter-tier modules. This approach enables significant run time reduction when thermal optimization is included in non-deterministic 3D-floorplaners that minimize peak temperature to generate thermally optimized 3D floorplans. Our results show that thermal quality factors, generated by our model, highly agree with factors generated by more accurate simulation-based thermal model, HotSpot. We achieve a correlation coefficient of 0.96 with the more accurate thermal model with an average speed up of 29X on a problem size of 64x64x4 evaluation grid for GSRC benchmarks. The proposed algorithm’s sensitivity to temperature difference between the 3D floorplans and success rate is also analyzed.