A Comprehensive Multi-Voltage Design Platform for System-Level Validation of Standard Cell Library

Akshay Kamath, Bharath Kumar, Sunil Aggarwal, Subramanian Parameswaran, Mitesh Goyal, Parag Lonkar, Somasunder Sreenath
Samsung Semiconductor India R&D


The quality assurance checks for standard cells are generally limited to validation at individual cell-level. In complex multi-voltage ASIC designs such as system-on-chips, where different types of standard cells are operating together, any inconsistency in the inference of cells in the synthesized netlist can go undetected and lead to increased design turn-around times. Validation of standard cells at system-level, therefore, becomes important to capture any design bugs during the early stages of standard cell library development. In this paper, we introduce a comprehensive design framework which emulates the usage of standard cells in a multi-voltage system-level environment and facilitates testing of their use-case correctness through functional and low-power simulation checks. Our design approach provides the distinct advantage of 100% coverage of logical standard cells of a given library in a single power-aware gate-level netlist. The proposed design platform is highly automated and scalable to different technology nodes which makes it a powerful setup to build system-level validation flows and help improve the overall quality of standard cell libraries.