A Low-Power LSTM Processor for Multi-Channel Brain EEG Artifact Detection

Hasib-Al- Rashid1, Nitheesh Kumar Manjunath1, Hirenkumar Paneliya1, Morteza Hosseini1, W. David Hairston2, Tinoosh Mohsenin1
1University of Maryland Baltimore County, 2Human Research and Engineering Directorate, US Army Research Lab


This paper proposes a low complexity Long Short-Term Memory (LSTM) based neural network architecture for detecting various artifacts in multi-channel brain EEG signals. Our proposed method consists of one average pooling layer of size 64, one LSTM layer having 12 units, one dense layer having 50 neurons and one output layer for binary classification.Our proposed method obtains average artifact detection accuracy of 93.1% which outperforms previous techniques based on Convolutional Neural Network (CNN) and Auto Regressive (AR) models for artifact detection in terms of classification accuracy.A complete hardware solution based on the proposed LSTM processor is designed in Verilog HDL, synthesized,and placed-and-routed on Artix-7 FPGA which consumes 17 mW power at operating frequency of 52.6 MHz. The proposed design is also implemented on NVIDIA JetsonTX2 platform.The experimental results indicate that our FPGA implementation outperforms the most efficient configuration of the ARM CPU by 13.5× in terms of power consumption. Compared to a previous work, our LSTM based FPGA hardware outperforms the CNN based FPGA hardware by 1.88× in terms of dynamic power consumption per classification.