NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework

Mohammad Saeed Abrishami1, Hao Ge1, Justin Calderon1, Massoud Pedram2, Shahin Nazarian1
1University of Southern California, 2USC


The shrinking of transistor geometries to 7nm and below as well as the increasing complexity of integrated circuits,significantly aggravate nonlinear design behavior. This demands accurate and fast circuit simulation to meet the design quality and time-to-market constraints. The existing circuit simulators which utilize lookup tables and/or closed-form expressions are either slow or inaccurate in analyzing the nonlinear behavior of designs with billions of transistors. To address these short-comings, we present NN-PARS, a neural network (NN) based parallelized circuit simulation framework with optimized event-driven scheduling of simulation tasks to maximize concurrency,according to the underlying GPU parallel processing capabilities. NN-PARS, replaces the required memory queries in traditional techniques, by parallelized NN-based computation tasks. Experimental results show that compared to a state-of-the-art current-based simulation method, NN-PARS reduces the simulation time by up to 130×. NN-PARS also provides high accuracy levels in signal waveform calculations, with less than 2% error, compared to HSPICE.