Mining Message Flow Specifications using Recurrent Neural Network for System-on-Chip Designs

Yuting Cao1, Mahesh Ketkar2, Parijat Mukherjee2, Hao Zheng1, Jin Yang3
1University of South Florida, 2Intel Corporation, 3Intel Corportation


Comprehensive specifications are essential for various activities across the entire validation continuum for system- on-chip (SoC) designs. However, the given specifications can be ambiguous and incomplete, or even contain inconsistencies or errors. This paper addresses this problem by developing a message flow specification mining approach that automatically extracts sequential patterns from SoC transaction-level traces such that the mined patterns collectively characterize system- level specifications for SoC designs. This approach exploits long short-term memory (LSTM) networks trained with the collected SoC execution traces to capture sequential dependencies among various communication events of those traces. Then, a novel algorithm is developed to efficiently extract sequential patterns on system-level communications from the trained LSTM models. Several trace processing techniques are also proposed to enhance the mining accuracy. We test the proposed approach on simulation traces of a non-trivial multi-core SoC prototype. Initial results demonstrate that the trained neural network model has a high correct rate on predicting the behavior of the SoC model.