The trend in the semiconductor industry is towards heterogeneous (polylithic) integration as opposed to monolithic integration. This is being driven by exorbitant costs as we scale the transistors beyond 7nm technology with large die areas. However, for heterogeneous integration (HI) to be viable, the performance needs to come close to that of monolithic integration as multiple dies are interconnected on an integrated packaging platform with fine lines/spaces and embedded circuitry. This requires optimization on several fronts including the architecture, chip/package co-design, managing signal/power integrity and minimizing area. This is a difficult task given the limitations of current methods when applied to non-convex response surfaces and the many parameters that are involved for tuning. In this talk I will focus on Machine Learning (ML) based optimization methods for designing and optimizing heterogeneous systems that are often times constrained by electrical, thermal and mechanical issues. These methods will be applied to 3DIC, high speed links, integrated voltage regulators and wireless systems.