SRAM access takes a signifi cant part of on-chip power consumption in many signal processing systems. Recon figurable data-adaptive SRAMs (RSRAM) can save considerable read power by utilizing data patterns. In these RSRAM designs, the column size (i.e., the number of cells in one column) of the cell array de fines the granularity of data pattern exploitation. However, the column size cannot be too small due to circuit constraints, which makes finer grained data features hidden and suppresses RSRAM's advantage of low-power read. In this paper, we propose a recon gurable SRAM architecture with column data segmentation (CDS-RSRAM) to break this limitation to exploit better data patterns without decreasing the column size. We partition data in one column into several segments and perform statistical analysis on every segment respectively. Each data segment has one exclusive flag bit to control its working mode while reading. This architecture can leverage data patterns at finer granularity and magnify RSRAM's advantage of low-power read. We also make a thorough overhead analysis and improve the mode decision strategy to minimize the power overheads. The simulation results show that compared with the original RSRAM, the proposed architecture saves up to 36.8% read power with 8.8% area overhead. Compared with 8T SRAM, the total power saving can be up to 77.1%.