Cryo-CMOS IC Design and Simulation for Quantum Computing

Jeroen van Dijk1, Pascal 't Hart1, Rosario Incandela1, Bishnu Patra1, Masoud Babaie1, Edoardo Charbon2, Fabio Sebastiano1, Andrei Vladimirescu3
1TU Delft, 2EPFL, Intel Corp, Kavli Institute Delft, 3University of California at Berkeley/ISEP


A quantum computer comprises a quantum processor and the associated control electronics used to manipulate the qubits at the core of a quantum processor. CMOS circuits placed close to the quantum bits and operating at cryogenic temperatures offer the best solution for the control of millions of qubits. The performance requirements of the electronics are very stringent and its design requires compact device models validated at 4 deg. K and the simultaneous optimization of both the circuits and the quantum system. This paper first presents the behavior validated by measurement of MOSFETs at cryogenic temperatures down to 100 mK and highlights the physical phenomena needing to be added to a compact simulation model. In addition to an accurate behavior description the effect of process variability and device matching is also addressed. For the electronics-quantum co-design and cooptimization the SPINE (SPIN Emulator) toolset was developed. It comprises a SPICE simulator enhanced with a Verilog-A model based on a Hamiltonian solver emulating the quantum behavior of single-electron spin qubits. A number of key circuit blocks of the control electronics were designed and implemented in a 40nm CMOS technology. Their design and measured performance will be highlighted. The compact models that were developed and used for the design are validated by comparing SPICE simulations with measured circuits at 4 deg. K.