A novel 2-stage pipelined architecture is proposed in this work to speed up the point multiplication in elliptic curve cryptography (ECC). This is achieved, at first, by reducing the number of clock cycles (latency) which is achieved through careful scheduling of computations involved in point addition and point doublings. Secondly, the arithmetic unit has been pipelined to achieve a smaller critical path. These two factors thus, help in reducing the time for one point multiplication computation. On the other side, the small area overhead for this design, gives a higher throughput/area ratio. The novel proposed architectures are synthesized on different FPGAs in order to compare with most relevant state-of-the-art work. The synthesis results of our proposed architectures over GF(2m) show that the proposed designs can work up to a frequency of 315, 311 and 309 MHz when implemented for m = 163, 233 and 283 bit key lengths on Virtex-7 FPGA. Finally, the novel architecture achieves the throughput/slice figures of 25.60, 9.02 and 7.30.