This paper presents a framework to automatically generate an implementation-aware functional coverage model. The generation of functional coverage model is based on the static elaboration of the design under verification (DUV) as well as the dynamic analysis of DUV simulation trace using data-mining techniques. Static analysis is used to extracts design attributes such as input/out ports, Finite State Machines (FSMs) and design variables that appear in the guard expressions of the design’s control flow. While strongly correlated design signals pairs as well as frequent patterns/sequences are detected as part of the miming step. Cone of influence analysis is utilized to guide the mining phase. Rule pruning and evaluation techniques are defined to reduce the huge number of generated properties from the mining of large designs’ simulation data. Strongly correlated design signals as well as useful design attributes are then fed as candidate cross-coverage bins and cover-points in the final functional coverage model. We propose a complete verification framework to validate the generated coverage model that utilizes Formal verification as well as mutation based testing. Our experimental results show that this approach helps in the generation of interesting coverpoints and cover properties that are common and widely used in today’s RTL designs.