Moore’s Law, i.e., transistor scaling and the reduction in cost-per-transistor, has been the primary driver of the semiconductor industry for the last fifty years, enabling system power and performance improvements. However, this relentless march towards smaller devices is facing severe opposition from non-negligible short channel effects, increasing variation, parasitics and lithography constraints. Efficient design-technology co-optimization (DTCO) enables us to push the limits of scaling, albeit, at a slower pace than historically possible. To continue to create compelling product scaling – improved power and performance while reducing cost – we need to explore alternate technologies such as 3D integration, neuromorphic computing, near-threshold computing, etc., and more directly co-optimize the device, circuits and associated systems. In this talk, we will discuss some of these across-abstraction co-optimization strategies and present potential solutions for future systems.