Three-dimensional integration (3D IC) technology has been gaining significant interest from the VLSI community for several years. However, layout-level explorations of the impact of 3D technology have only recently been introduced. This work examines both static and dynamic power-supply noise in a layout-level 3D design prototype, and the impact of possible 3D-specific changes to the power-supply network design and topology. Our results show that distributing power-supply TSVs throughout the design with finer pitch than the C4 supply bumps lowers both IR-drop and dynamic noise in our 3D system. In fact, using a distributed TSV topology lowers dynamic noise by 13.3% compared to a 2D system with less total power dissipation. We also show several other 3D-specific supply network changes and their impact on both IR-drop and dynamic noise.