Double-patterning lithography is a choice for critical layers in 32 nm and 22 nm technologies. Double patterning lithography techniques require additional masks to manufacture a single device layer. Consequently, double-patterning lithography brings overlay as a challenge that introduces additional variability to gate coupling capacitances. This additional variability may negatively impact circuit performance. We provide variational device and circuit analysis methods for double-patterning lithography. We demonstrate our methodology using TCAD and circuit simulations in a 32 nm technology. Proposed results shed light on understanding the possible impact of overlay on device and circuit performance.