Engineering Change Order (ECO), is an effective technique for fixing circuit functionality and timing problems after the placement stage. We proposed a new approach to solve the functionality and timing problems simultaneously by rerouting the netlist to the spare cells. The proposed approach includes two stages (1) functional change with timing consideration and (2) timing optimization. In the first stage, a spare cell selection algorithm is designed to select proper spare cells which can solve not only the functionality but also the timing violation problems. The second stage we conduct timing analysis to find paths that have timing violation and solve those paths by applying gate sizing and buffer insertion techniques. Experimental results are based on five industry benchmarks. The results show that our approach is effective and efficient in fixing the functional change problem and timing optimization problem.