Circuit-level delay modeling considering both TDDB and NBTI

Hong Luo1,  Xiaoming Chen1,  Jyothi Velamala2,  Yu Wang1,  Yu Cao2,  Vikas Chandra3,  Yuchun Ma4,  Huazhong Yang1
1Dept. of E.E., TNList, Tsinghua Univ., Beijing, China, 2Dept. of E.E., Arizona State Univ., USA, 3ARM R&D, San Jose, USA, 4Dept. of C.S., TNList, Tsinghua Univ., Beijing, China

Abstract

With aggressive scaling down of the technology node, the time-dependent dielectric breakdown (TDDB) and negative biased temperature instability (NBTI) are becoming key challenges for circuit designers. Both TDDB and NBTI significantly degrade the electrical characteristic of the CMOS devices. A delay model considering TDDB and NBTI is proposed in this paper. The output degradation of the breakdown gate is considered in circuit-level delay analysis. Traditionally, it is considered the TDDB degradation always degrades the circuit delay. However, this paper shows the TDDB effect may boost up the circuit speed. The spatial correlation of TDDB effect is also demonstrated in this paper and shows the difference of 40% in circuit delay depending on the location of the breakdown gate in the signal path.