With the increase in circuit frequency and supply voltage scaling, a robust power network design is essential to ensure that the circuits on a chip operate reliably at the guaranteed level of performance. Traditionally the power network analysis has its main focus on IR-drop effects. However, IR-drop analysis approaches have strong dependence on the input vectors and may require a tremendously long execution time. In this paper, we propose a novel and fast power network analysis method which calculates the effective resistance between all power pads and power grids. This method explores huge parasitic power networks and detects hot spots with an abnormal effective resistance value resulted from gross errors in the post-layout power network. We currently use the proposed method for our memory and DDI circuits to validate the post-layout power network quickly. We developed our method by using multi-thread and multi-process techniques, resulting in up to 50 times speed improvement.