Multi-finger transistor layout is widely used in CMOS circuit designs. Comparing with single-finger transistor layout, its main features include effectiveness in reducing circuit physical size and improving device matching. However in CMOS ring oscillator design, considerable performance discrepancies are found between multi-finger transistor layout and single finger transistor layout. Despite such fact, there exists no analysis method that can be used to illustrate oscillator performance differences resulted from these two layout manners. In this paper, an analytic model is developed to characterize multi-finger transistor and single-finger transistor oscillator designs. The specific focuses are on oscillator output frequency and phase noise specifications. For model validation, oscillator circuits are designed using IBM 0.13um CMOS technology and simulated with Cadence Spectre simulator.