The extent to which the 6T SRAM bit cell can be perpetuated through continued scaling is of enormous technological and economic importance. Understanding the growing limitations in lithography, design and process technology, coupled with the mechanisms which drive systematic mismatch, provides direction in identifying more optimum solutions. We propose an alternative, ultra-thin (UT) SRAM cell layout topology as a means to address future manufacturability and the challenging bit cell design constraints facing the most advanced CMOS process technologies today. Compared to the industry standard 6T topology, the newly proposed cell offers: 1) a lower bit line capacitance, 2) reduced M1 complexity and 3) notchless design for improved resistance to alignment induced device mismatch.