Addressable test array needs switches to select and isolate testing structures; however, switches occupy extra chip area and limit the array size due to additional switch leakage. In this paper, we implement the switch by NMOS transistor, thus improve the design of addressable test array on array size, measurement accuracy as well as area efficiency. Simulations in a 65 nm technology have verified this technique’s feasibility and reliability. A large 64x64 array using this 65 nm technology has been designed in a systematic flow and manufactured for silicon data, which further confirms the effectiveness of the presented technique.