A novel method to characterize CMOS process fluctuations in subthreshold current mirrors (SCM) is reported in this paper. The proposed model is succinct in methodology and calculation complexity comparing to the reported statistical models, however, provides favorable estimations of CMOS process fluctuations on the SCM circuit, which makes it being promising for engineering applications. The model statistically abstracts physical parameters, which depend on IC process, into random variables with certain mean values and standard deviations, while aggregating all the random impacts into a discrete martingale. The correctness of proposed method is experimentally verified by an SCM circuit implemented in SMIC 0.18 um CMOS 1P6M mixed signal process with a conversion factor of 100 over an input range from 100 pA to 1 uA. The proposed theory successfully predicted the 10% of die-to-die fluctuation measured in experiment, and also suggested the ~1 mV of threshold voltage standard deviation over a single die, which meets the process parameters suggested by the design kit from the foundry. The deviations between calculated probabilities and measured data are less than 8%. Meanwhile, pertinent suggestions to high fluctuation tolerance subthreshold analog circuits design are also made and discussed.