Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling has been provably one of the most effective techniques to achieve low power specifications. On the other hand, as the feature size of logic gates is becoming smaller, the effect of soft error rates caused by single event upsets is becoming exponentially greater. Lowering supply voltage as a means of power reduction, increases soft error rates caused by SEU for two reasons: Lower voltage makes digital circuits more prone to soft errors and reduction in supply voltage, increases the duration of process which increases the chances of being hit by SEU. In this paper, we propose an optimal methodology for DVS on task graphs with consideration for SEU. 1) We consider the effects of voltage on SEU and incorporate this dependency in our formulation to develop a new method for energy optimization under SEU constraints and reliability improvement. 2) We propose a convex programming formulation that can be solved efficiently. 3) We provide linear sized problem formulation in the DVS problem under study. We show the effectiveness of our method by simulation on TGFF bench marks.