Session 7C

San Martin Room

3:30PM – 5:35pm

Robust Design under Parameter Variations

Chairs:    Ravi Joshi, IBM

Sarma Vrudhula, Arizona State University

3:30pm

Introduction

3:35pm

7C.1       

A New Method for Robust Design of Digital Circuits

Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, Mark Horowitz, Stephen Boyd, Stanford University

4:05pm

7C.2       

Analysis and Synthesis of Staggered Twisted Bundle for Crosstalk Reduction

Hao Yu, Lei He, University of California at Los Angeles

4:35pm

7C.3       

Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations

Wei Ling, Yvon Savaria, l'École Polytechnique de Montréal

5:05pm

7C.4

Impact of Interconnect Process Variations on Memory Performance and Design

Andres Teene, Bob Davis, Ruggero Castagnetti, Jeff Brown, Shiva Ramesh, LSI Logic