Session 4A

San Carlos Room

5:15pm – 6:50pm

DFM for Circuit Design

Chairs:    Sani Nassif, IBM

Nagib Hakim, Intel

5:15pm

Introduction

5:20pm

4A.1       

Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE

Xiaojun Li, B. Huang, J. Qin, X. Zhang, M. Talmor, Z. Gur, Joseph B. Bernstein, University of Maryland

5:50pm

4A.2       

Modeling Layout Effects for Sensitivity-based Analog Circuit Optimization

Henry H. Y. Chan, Zeljko Zilic, McGill University

6:20pm

4A.3       

In-Circuit Self-Tuning of Clock Latencies

Kambiz Rahimi*, Chris Diorio**, *Impinj Inc., **University of Washington

6:35pm

4A.4       

Statistical Analysis of Clock Skew Variation in H-tree Structure

Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera, Osaka University, Japan