Session 1D

City Foyer

10:30am – 3:15pm

Poster Session

Chairs:    James Lei, Altera

Israel Koren, University of Massachusetts Amherst

1D.1       

Non-Charge-Sheet Core and Architecture of BSIM5

Jin He, Jane Xi, Mansun Chan, Hui Wan, Mohan Dunga, Babak Heydari,, Ali M. Niknejad, Chenming Hu, University of California, Berkeley

1D.2       

Integration of DFM Practices in Design Flows

L.Riviere Cazaux, Freescale Semiconductors

1D.3       

How Circuit Analysis and Yield Optimization Can Be Used to Detect Circuit Limitations before Silicon Results

Carlo Roma, Pierluigi Daglio, Guido De Sandre, Marco Pasotti, Marco Poles, STMicroelectronics

1D.4       

Leakage Current Modeling in Pd SOI Circuits

Mini Nanua*, David Blaauw**, MI, Chanhee Oh***, *Sun Microsystems, Austin, TX, **University of Michigan, ***Nascentric, Austin, TX

1D.5       

A Balanced Scorecard for Systemic Quality in Electronic Design Automation: An Implementation Method for an EDA Company

Jasjeet Kaur, Mentor Graphics

1D.6       

RCL Characterization and Modeling of X Architecture Diagonal Wires for VLSI Design

Narain D. Arora, Li Song, Santosh Shah, Kalyan Thumaty, Aki Fujimura, Victor Chang*, S. Y. Cho*, Cadence Design Systems, *TSMC

1D.7       

A Technique for Designing Totally Self-Checking Domino Logic Circuits

C.K. Tang, P.K. Lala, J.P. Parkerson, University of Arkansas

1D.8       

Early Assessment of Leakage Power For System Level Design

C. Talarico, B.S. Pillilli, K.L.Vakata. J.M. Wang, University of Arizona

1D.9       

Technology Mapping For Reliability Enhancement in Logic Synthesis

Zhaojun Wo, Israel Koren, University of Massachusetts Amherst

1D.10     

Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays

Diaaeldin Khalil*, Mohamed Dessouky*, Vincent Bourguet**, Marie-Minerve Louërat**, Andreia Cathelin***, *Hani Ragai

Ain Shams University, Egypt, **University of Paris 6, France, ***STMicroelectronics, France

1D.11     

Closing the Gap Between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders

Behnam Amelifard*, Farzan Fallah**, Massoud Pedram*, *University of Southern California, **Fujitsu Laboratories of America, Inc.

1D.12     

Capacitance and Yield Evaluations Using a 90-Nm Process Technology Based on the Dense Power-Ground Interconnect Architecture

Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda, Semiconductor Technology Academic Research Center, Japan

1D.13     

Testing for Resistive Shorts in FPGA Interconnects

Haixia Gao, Yintang Yang, Xiaohua Ma, Gang Dong, Xidian University, P.R. China

1D.14     

TED Thermo-Electrical Designer: A New Physical Design Verification Tool

Sokolowska Ewa, Barszcz Marek, Kaminska Bozena, Pultronics Inc.

1D.15     

A Fast Lithography Verification Framework for Litho-Friendly Layout Design

Yong-Chan Ban, Soo-Han Choi, Ki-Hung Lee, Dong-Hyun Kim, Ji-Suk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong, Samsung,  South Korea

1D.16     

Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate

Harmander S. Deogun, Dennis Sylvester, David Blaauw, University of Michigan

1D.17     

Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer

Hua Xiang, Kai-Yuan Chao, Martin D.F. Wong, IBM

1D.18     

Design of a 10-bit TSMC 0.25um CMOS Digital to Analog Converter

J. Huynh, B. Ngo, M. Pham, Lili He, San Jose State University

1D.19     

A High-Performance SRAM Technology with Reduced Chip-Level Routing Congestion for SOC

R. Castagnetti, R. Venkatraman, B. Bartz, C. Monzel, T. Briscoe, A. Teene, S. Ramesh, LSI Logic

1D.20     

Design and Evaluation of a Security Scheme for Sensor Networks

Khadija Stewart, Themistoklis Haniotakis, Spyros Tragoudas, Southern Illinois University Carbondale

1D.21     

A Minimum Cut Based Re-Synthesis Approach

M. Welling, S.Tragoudas, H. Wang, Southern Illinois University Carbondale

1D.22     

Analysis for Complex Power Distribution Networks Considering Densely Populated Vias

Young-Seok Hong, Heeseok Lee, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong, Samsung Korea

1D.23     

Buffer Planning Algorithm Based on Partial Clustered Floorplanning

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Tsinghua University, China

1D.24     

Issues and Challenges in Ramp to Production

Ravi Arora, Arun Shrimali, Anand Venkitachalam, Texas Instruments