ISQED05 Plenary Session 1P

Tuesday March 22, 2005

Plenary Session 1P

Donner Pass Room

8:30am - 10:15am


Co-Chairs:    Kris Verma

Silicon Valley Technical Institute

Kenneth Shepard

Columbia University 



Introduction & Announcements



1P.1 Enabling True Design for Manufacturability


John Kibarian

President & CEO, PDF Solutions


Without any doubt, Design For Manufacturability has been the hottest buzzword for the last couple of years. This is quite justifiable by the enormous challenges in nanometer technology nodes and ever increasing design-process interactions. As a result, virtually all EDA companies have focused on providing the "DFM Solutions".  Since the concept of DFM covers an extremely broad spectrum of tasks from the system level all the way to the manufacturing process, many of these DFM solutions are just the re-labeled design verification tasks. 

In this talk, we will provide a more thorough classification of various DFM activities with the emphasis on the design tasks. We will also discuss the necessary condition to enable true DFM, i.e.,   the comprehensive characterization of the design-process interactions. We will present a complete process characterization methodology that is capable of extracting all the salient process variations for a full set of product design attributes. We will illustrate our talk by showing the yield loss Pareto for the leading technology nodes that will cover all the dominant yield loss phenomena including random, systematic and parametric mechanisms. We will also demonstrate example of design flows that take advantage of such a comprehensive characterization together with silicon results demonstrating the advantages of true DFM.




1P.2 Recent progress and remaining challenges in pattern transfer technologies for advanced chip designs


Ashok K. Sinha

Sr. VP & GM

Applied Materials, Inc


Even as the Moore's law continues to drive "tiny technologies" through relentless scaling, the main technology driver for semiconductor chips has evolved from DRAMs to Microprocessors to FPGAs. The underlying metrics have evolved from bits per chip and cost per bit for computers to functions per chip and cost per function for consumer products. This talk will review the remarkable progress that has been made in enabling pattern transfer technologies, including mask design, lithography enhancements and precision etching on the new 300mm wafers for an increasingly wide variety of new materials. However, there is a cost associated with all this and the cost-benefit tradeoffs will almost certainly drive new inflections in the entire food chain, which I will try to identify.




1P.3 Shifting Perspectives on DFM


Janusz Rajski

Chief Scientist, Design Verification and Test Division 

Mentor Graphics

Nanometer technology has ushered in new and significant yield and manufacturing considerations and constraints. The lack of major increase in yield improvement between the 350nm and 180nm nodes suggests that the yield loss mechanisms are not only increasing in numbers, magnitude, and complexity at each successive generation, but they are increasing at a rate fast enough to largely offset ‘cosmetic’ improvements in tools and methodologies.

If EDA tools are to assist the semiconductor industry at the 90nm and 65nm nodes, there must be profound changes to existing tools, and the introduction of new technologies that allow designers to consider and optimize for manufacturing at each stage of the design, verification, tapeout and test process.


Home| Conference| Committee| Sponsors| Resources| Archive| News

International Society for Quality Electronic Design (ISQED Org.)
Copyright © 1998-2005 ISQED. All rights reserved.
Revised: March 10, 2005