Session EP1

Panel Discussion & Dinner

Donner Pass Room

6:30pm - 8:30pm

IP Creation and Use 

What roadblocks are ahead or it is just clear and bumpy road?

Panel Organizer: Pallab Chatterjee, SiliconMap

Panel Moderator: Stephen Ohr, EETimes

As custom (Analog & MS device level) design progresses into smaller process geometries, companies are faced with many challenges with new names - DFM, DFY, DIR, OPC/RET/MDP, DR and new tools in the EDA/CAD space. A great many of the issues have been around since the start of the IC industry; they are just getting new attention. This panel of seasoned veterans and technology innovators will discuss the change in the scope of the work effort involved in custom design in the 180-47nm process technologies and if the design superhighway has turned into a dead end with insurmountable roadblocks or simply a very bumpy side road in need of significant repair and upgrade.

Panelists:

Joachim Kunkel, Vice President of Engineering, DesignWare, Synopsys

Naveed Sherwani, Co-Founder, President & CEO of Open-Silicon

Kevin MacLean, Vice President, PDF Solutions

Jeff Lewis, Ciranova

Mark Rubin, Intersil Corp

Ken Brock, Silvaco Data Systems