Session 6A

3:30pm - 5:20pm

DFM Design Techniques

Co-Chairs

Sani Nassif, BM
James Tschanz, Intel

3:30pm

Introduction  

3:35pm

6A-1    Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well Adaptive Body Biasing (IWABB), Justin Gregg and Tom Chen

4:05pm

6A-2    Concurrent Error Detection for Combinational and Sequential Logic via Output Compaction
Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris

4:35pm

6A-3    Cost Model Analysis of DFT Based Fault Tolerant SOC Designs
Karthik Sundararaman,Shambhu Upadhyaya,Martin Margala

5:05pm

6A-4    Managing Derivative SoC Design Projects to Better Results
Lane Albanese

5:20pm

6A-5    IPQ: IP Qualification for Efficient System Design
Hans-Jürgen Brand Steffen Rülke Martin Radetzki